1. Field of the Invention
The present invention relates to electronic switches. In particular, the present invention relates to semiconductor switches, including those formed of one or more metal-oxide-semiconductor (MOS) transistors. More particularly, the present invention relates to N-type MOS (NMOS) field effect transistor (FET) bus switches.
2. Description of the Prior Art
Developments in semiconductor technology have created the capability to produce low-cost, highly reliable switches that are, effectively, implementations of mechanical relays. They have been found to be of particular use, when implemented, as single pole, single throw, type relays, but are not limited thereto. Semiconductor switches are being used more and more as replacements for the prior mechanical relays, due to the high switching speed available as well as their ability to transfer relatively high currents without failure. These switches are often referred to as transfer gates or pass transistors as they employ the characteristics of transistors--usually MOS transistors--to either permit or prevent the passage of a signal.
It is well known that switches are widely used in many fields. They are used in all variety of large- and small-scale consumer products, including, but not limited to, automobiles and home electronics. They can be and are used as analog routers, gates, and relays. They are used as digital multiplexers, routers, and gates as well.
A number of prior-art transfer gates have been developed for digital and analog applications. Recent innovations have provided methods for operation at lower power supply potentials such as 3.3 Volts and 2.5 Volts, while providing some method of maintaining isolation when input values go beyond high- and low-potential power rail values. That is, when a transfer gate input potential exceeds the high-potential rail Vcc positively, or it exceeds the low-potential rail GND negatively. One such device that has been in relatively common use is shown in FIG. 1
A complementary pair of transistors, NMOS transistor M1 and PMOS transistor M2 conduct signals between nodes A and B, where each of those nodes is couplable to an extended circuit. When a control signal OEN (shown in FIG. 1 associated with node A as the input for purposes of illustration only, but which can also be associated with node B as the input) is a logic "high" or "1," transistor M1 is turned on, and as a result of the inversion produced by inverter 11, transistor M2 is also on. In this condition, the two transistors are "on" and the potential at node B is essentially the same as the potential at node A. When OEN is at a logic "low" or "0," both transistors are off and there exists a high impedance for the transfer of any signal between nodes A and B. This is true for all potentials at node A or B that are less than the potential of high-potential power rail Vcc and greater than low-potential power rail GND. However, when either the input or the output node is greater than Vcc or less than GND, the potential associated with the typical logic low at the gate of transistor M1 and a typical logic high at the gate of M2 is insufficient to keep those transistors off. For a potential greater than Vcc, M2 will turn on, for a potential less than GND, M1 will turn on, irrespective of the logic level applied at input OEN. As a result, an overvoltage condition at either the input or the output will cause M1 and M2 to permit a signal to pass through that the OEN deems should be blocked. An undervoltage condition will likewise be passed under the same OEN condition.
For the purpose of this disclosure, the terms "overvoltage" and "undervoltage" mean the potential variations noted that occur under static (DC) conditions as well as dynamic (AC) conditions. For that reason, overvoltage may be used interchangeably with overshoot. Similarly, undervoltage may be used interchangeably with undershoot. Passage of any of those conditions when OEN deems such conditions should be blocked is undesirable.
A device designed to resolve at least one portion of the problems associated with the complementary transfer gate of FIG. 1 is shown in FIG. 2. The device involves removal of PMOS transistor M2, leaving NMOS transistor M1 coupled between nodes A and B, where node A is the input from, or output to, a first extended circuit, and node B is the input from, or output to, a second extended circuit. As before, control node OEN is designed to control enablement of M1. In operation, a logic level high from OEN to the gate of M1 renders M1 on and thereby permits a signal to pass between nodes A and B. A logic level low turns M1 off and blocks the transfer of the signal between A and B. Elimination of transistor M2 resolves the problem when the potential at node A or node B exceeds Vcc because that transistor is not there to be turned on. Unfortunately, that does not eliminate the possibility that the transfer gate will turn on when it should be off under conditions of negative voltage exceeding GND.
An alternative and more complex prior transfer gate is shown in FIG. 3. That device includes a series pair of NMOS pass transistors. When OEN transmits a logic low or "off" signal, the circuit of FIG. 3 will remain off, even when Vcc and GND are exceeded. Thus, this circuit is a reasonable alternative to the circuit shown in FIG. 2. However, the effective drain-source resistance R.sub.DS associated with using the two NMOS transistors in series is several hundred ohms dependent upon the particular characteristics and coupling of the transistors. While that resistance is acceptable in analog devices, it is not so in digital systems where the RC time constant is a critical consideration in the rate of operation of a circuit. Therefore, this transfer gate would not be particularly suitable for digital circuitry that operates at increasingly faster rates.
U.S. Pat. No. 5,808,502 issued to Hui et al. describes some of the problems noted in association with one-transistor and two-series transistors used to transfer selected signals between nodes or pads. Hui provides a solution of increasing the potential supplied to the gates of the transistors through the use of a charge pump. Such a solution has its own problems, including the noise problem that Hui seeks to solve through the addition of a capacitor coupled to the charge pump. However, the Hui solution involves the use of series transistors to maintain isolation. Series transistor approaches penalize the user since the capacitance of the enabled series transistor transfer gate is much higher than that of a single transistor transfer gate. The capacitances of both FET devices are present on the I/O ports of the transfer gate.
It would be desirable to have a transfer gate operating with a single NMOS transistor as the FET switch substantially as shown in the circuit of FIG. 2. This would address the problems of relatively high resistance and relatively high capacitance experienced at the output of the switch circuit when the circuit is substantially as shown in FIG. 3. However, the prior single NMOS switch of FIG. 2 is unacceptable during undershoot conditions in that there is a parasitic diode connected between either the source or drain of the transistor and its bulk. The bulk is tied to the low-potential power rail usually identified as ground. During voltage undershoot conditions at the low-potential rail, the parasitic diode conducts current from ground to either the input node or the output node, depending upon which is at a potential that is less than ground potential. Under that condition, current will move from the output node to the input node, thereby causing a disruption of signal transmission otherwise occurring at the output node. This can occur independent of the condition of the enable signal at OEN.
Two characteristics of the physical structure of the single NMOS FET switch cause this clearly undesirable parasitic conduction condition. The first is the formation of a parasitic bipolar NPN transistor. The second is the unintended turning on of the NMOS FET switch in certain undershoot situations. With regard to the first condition, the drain (N-type collector), transistor bulk (P-type base), and source (N-type emitter) form the NPN transistor. Transistor fabrication steps currently in use in sub-micron processes can yield in this common-base parasitic bipolar transistor a current gain that is the equivalent of a common-emitter gain (.beta.) of about 10. Thus, during an undershoot condition, the relatively small current moving from the low-potential rail to the more negative input node yields a ten-fold increase in the undesired parasitic current moving from the output node to the input node. Of course, in an ideal FET switch there should be no current flowing from the output node to the input node unless specifically enabled.
The other undesirable condition associated with the parasitic diode of the prior single-FET switch relates to the unintended turning on of the FET switch during an undershoot event. Specifically, this occurs when there is enough current generated in the substrate of the transistor to cause a voltage drop in the transistor's bulk that is enough to turn the transistor on. If the current developed between the low-potential rail and a lower-potential circuit node causes a drop across the substrate/bulk resistance that is at least the equivalent of the threshold turn-on potential V.sub.TN of the transistor, the transistor will conduct current from one circuit node to the other.
It may be seen that it is necessary to isolate the primary FET bulk from ground when the switch is disabled in order to prevent the parasitic NPN bipolar transistor condition. However, in order to address the second problem condition, it is necessary to keep the primary transistor's gate potential substantially the same as its bulk potential. A related circuit that solves these problems in a passive arrangement is shown in FIG. 4. In that circuit, the switch 10 includes a first arbiter circuit 20, a second arbiter circuit 30, a pseudo low-potential rail PGND, a bulk potential coupling circuit 40, and transfer transistor M1. Enable controller circuit 50, supplied by a standard high-potential power rail Vcc, is used to define a selectable signal to activate the transfer transistor M1. An enable signal coming from a control circuit (not shown) by output enable node OEN is coupled to the gate of M1 and the pseudo-low potential power rail PGND through circuit 50. Transistor M1 is the primary regulator of the transfer of a signal between nodes A and B and is an N-type MOS transistor formed with an isolated P-type well. Either of node A or node B may be an input node or an output node, dependent upon the direction of the signal passing between the external circuitry coupled to those two nodes.
Though the circuit of FIG. 4 addresses the prior problems of undershoot and overshoot situations, it nevertheless it requires a triggering condition (undervoltage or overvoltage) of about one threshold potential drop (Vt) that may be about 0.6V. That is, a differential signal of sufficient magnitude is required in that circuit to activate the comparators sufficiently to tie the transfer transistor's bulk to the pseudo-low potential power rail. In those situations where it is desirable to address the over/under problem more quickly, there may be an undesirable lag associated with the solution of the circuit of FIG. 4. It would therefore be preferable in some situations to activate the connection to the pseudorail more quickly than is possible through the passive circuit of FIG. 4.
Therefore, what is needed is a FET switch that isolates the primary FET bulk from ground (for undervoltage conditions) and that maintains the primary FET's gate potential at or about the potential of that transistor's bulk. What is also needed is such a FET switch that offers less resistance and capacitance than prior switches. Yet further, what is needed is a FET switch that may be selectably activated to isolate a node from overvoltage or undervoltage potential deviations that are relatively small.